Abstract

This study presents a hardware countermeasure that integrates two distinct types of random number generators. Recently, several effective time-based countermeasures against side-channel analysis (SCA) have relied on FPGA-specific primitives, such as Xilinx Digital Clock Managers (DCM) and Mixed-Mode Clock Managers (MMCM). However, these solutions lack portability to ASIC platforms. To address this, we propose a Hybrid Dynamic Gold code-based countermeasure that is easily implementable across both ASIC and FPGA platforms. Fabricated in the 180-nm CMOS process, the circuit occupies a total area of 408, 077 μm2 , representing a negligible overhead of only 1.007× in power and 1.012× in hardware compared to the unprotected design. Experimental results confirm that the generated random initial states successfully pass Process, Voltage, and Temperature (PVT) conditions with standard statistical test suites. Furthermore, the proposed countermeasure demonstrates high resistance to conventional Correlation Power Analysis (CPA), maintaining security even with 5 million traces. CPA with an advanced alignment preprocessing step, called the amplitude peak location algorithm, requires 500,000 power traces to achieve a global success rate of 81.25 % (i.e., revealing 13 of 16 bytes).